For systems that require strong security and safety guarantees, an open ISA provides the foundation of a completely understood supply chain. Open architectures such as RISC-V provide transparency down to the deepest levels of a system.
Organizations like RISC-V International collaborate with dozens of companies, academic institutions, and passionate individuals to propel the ecosystem forward. Since its first publication from UC Berkeley in 2011, adoption of RISC-V has seen incredible growth. The open source nature of the ISA has allowed global innovation and creativity in much the same way Open Source revolutionized software. RISC-V is a free, open CPU instruction set architecture (ISA) that is revolutionizing hardware. We'll also see how to test RISC-V Linux programs using qemu (a hardware emulator).īefore we dive in, let's start with a ~2 minute demo of how to run Ockam's end-to-end encryption example on Microchip's PolarFire SoC Icicle kit (which includes 4 RISC-V cores).
In this hands-on guide, we'll introduce RISC-V, and show how to cross compile a Rust example of Ockam for RISC-V Linux systems. End-to-end encryption and mutual authentication for distributed applications.